1. Field of the Invention
The present invention relates to an epitaxial layer and a method of forming an epitaxial layer, and more particularly to an epitaxial layer including silicon, carbon, phosphorous and germanium and a method of forming the same.
2. Description of the Prior Art
With the trend of miniaturization of semiconductor device dimensions, the scale of the gate, source and drain of a transistor has dropped in accordance with the reduction of the critical dimension (CD). Due to the physical limitation of the materials used, the decrease of the gate, source and drain scale results in the diminution of the number of carriers that determine the magnitude of the current in the transistor element, which can adversely affect its performance. Accordingly, in order to boost up a metal-oxide-semiconductor (MOS) transistor, increasing the carrier mobility is an important consideration in the field of current semiconductor technique.
In the conventional technologies, a strained semiconductor substrate is used to provide biaxial tensile stresses to increase the carrier mobility. A silicon-germanium (SiGe) layer is formed on the silicon substrate, and a silicon layer is further formed on the SiGe layer to constitute the strained semiconductor substrate. The lattice constant of silicon (Si) is 5.431 angstroms (A), and the lattice constant of germanium (Ge) is 5.646 A. When the silicon layer is disposed on the SiGe layer, lateral stress is induced in the silicon layer due to the lattice constant difference, so this silicon layer can serve as a strained silicon layer. The strained silicon layer facilitates the formation of a gate dielectric layer of high quality, and provides stress to the channel region of a transistor for enhancing carrier mobility. Furthermore, a selective epitaxial growth (SEG) process can also be used to form a strained silicon layer; after the formation of the gate, a silicon-germanium (SiGe) layer is further formed in the predetermined location of the source/drain region at two sides of the gate structure to provide compressive stress in order to boost up a PMOS transistor; or a silicon-carbide (SiC) layer is further formed in the predetermined location of the source/drain region at two sides of the gate structure to provide tensile stress in order to boost up a NMOS transistor.
A source/drain region of a NMOS transistor includes n-type dopant doped strained silicon layer such as phosphorous (P) doped silicon-carbide layer. The atomic radius of phosphorous (1.26 angstroms) and the atomic radius of carbon (0.91 angstroms) are smaller than the atomic radius of silicon (1.46 angstroms), so phosphorous doped silicon-carbide layer may not be formed properly on the (111) crystallographic planes of the silicon wafer due to the atomic radius difference. Therefore, the recesses at two sides of the gate structure may not be filled up with the phosphorous doped silicon-carbide layer to form the complete source/drain region, which adversely affect the performance of the NMOS transistor. Consequently, how to improve an epitaxial layer process for forming an epitaxial layer including elements having different atomic radiuses is still an important issue in this field.